1. Field of Invention
The present invention relates to devices, decoders, programs, and methods for performing control related to the power consumption of computing units. More particularly, the invention relates to a power control device for a computing unit, a power-saving decoder, a power control program for a computing unit, and a power control method for a computing unit optimal for saving power.
2. Description of Related Art
Computing (arithmetic) operation processors operate at a constant clock frequency irrespective of the contents of MPEG (Moving Picture Experts Group) data when decoding the MPEG data. There are computing (arithmetic) operation processors for saving power. Such computing (arithmetic) operation processors each have an operation load monitoring circuit for monitoring an operation load on the corresponding computing (arithmetic) operation processor. The operation load monitoring circuit adjusts the clock frequency on the basis of the monitoring result.
MPEG data includes video data and music data. Video data includes a predetermined number of frames of frame data, each frame forming one frame of a video image. The arithmetic operation processor decodes the frame data in units of frame data when playing the video image on the basis of the video data. The decoding must be completed within a predetermined frame rate.
Such arithmetic operation processor can operate at a constant clock frequency irrespective of the contents of MPEG data. If decoding of frame data is completed within a frame rate, the arithmetic operation processor operates at a high clock frequency for the remaining time of the frame rate although the arithmetic operation processor does not need to perform operations. As a result, the power consumption of such a device can be large.